[firefly] [PATCH v2] x86/pci: checkpatch.pl cleanup

[Valentina Manea]

This patch fixes warning and errors found by checkpatch.pl:

* replace asm/acpi.h, asm/io.h and asm/smp.h with linux/acpi.h,
linux/io.h and linux/smp.h respectively
* remove explicit initialization to 0 of a static global variable
* replace printk(KERN_INFO ...) with pr_info
* use tabs instead of spaces for indentation
* arrange comments so that they adhere to Documentation/CodingStyle

Signed-off-by: Valentina Manea <valentina.manea.m at gmail.com>
---
Changes since v1:
* cleaned up all checkpatch.pl errors according to Ingo's review 

 arch/x86/pci/mrst.c |   17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index 6eb18c4..2126dc6 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -23,11 +23,11 @@
 #include <linux/ioport.h>
 #include <linux/init.h>
 #include <linux/dmi.h>
+#include <linux/acpi.h>
+#include <linux/io.h>
+#include <linux/smp.h>
 
-#include <asm/acpi.h>
 #include <asm/segment.h>
-#include <asm/io.h>
-#include <asm/smp.h>
 #include <asm/pci_x86.h>
 #include <asm/hw_irq.h>
 #include <asm/io_apic.h>
@@ -43,7 +43,7 @@
 #define PCI_FIXED_BAR_4_SIZE	0x14
 #define PCI_FIXED_BAR_5_SIZE	0x1c
 
-static int pci_soc_mode = 0;
+static int pci_soc_mode;
 
 /**
  * fixed_bar_cap - return the offset of the fixed BAR cap if found
@@ -235,7 +235,7 @@ struct pci_ops pci_mrst_ops = {
  */
 int __init pci_mrst_init(void)
 {
-	printk(KERN_INFO "Intel MID platform detected, using MID PCI ops\n");
+	pr_info("Intel MID platform detected, using MID PCI ops\n");
 	pci_mmcfg_late_init();
 	pcibios_enable_irq = mrst_pci_irq_enable;
 	pci_root_ops = pci_mrst_ops;
@@ -250,9 +250,10 @@ int __init pci_mrst_init(void)
 static void pci_d3delay_fixup(struct pci_dev *dev)
 {
 	/* PCI fixups are effectively decided compile time. If we have a dual
-	   SoC/non-SoC kernel we don't want to mangle d3 on non SoC devices */
-        if (!pci_soc_mode)
-            return;
+	 * SoC/non-SoC kernel we don't want to mangle d3 on non SoC devices.
+	 */
+	if (!pci_soc_mode)
+		return;
 	/* true pci devices in lincroft should allow type 1 access, the rest
 	 * are langwell fake pci devices.
 	 */
-- 
1.7.10.4